Push-and-pull driver circuit for driving an H-bridge coupled to a two-terminal inductive load

ABSTRACT

A write driver for a two-terminal inductive load comprises an H-bridge switching circuit and a push-pull driver circuit. The H-bridge switching circuit responds to a first mode to conduct a current in a first direction through the inductive load and responds to a second mode to conduct the current in a second direction through the inductive load. The push-pull driver circuit responds to the first mode to push a charge current into a first control node of the H-bridge and responds to the second mode to pull a discharge current from the first control node. In one form, the write driver includes a second push-pull driver circuit responsive to the first mode to pull a discharge current from a second control node and to the second mode to push a charge current into the second control node.

BACKGROUND OF THE INVENTION

The present invention relates to write drivers for magnetic transducers. More particularly, it pertains to a write driver circuit for a two-terminal inductive transducer having improved switching performance.

Inductive magnetic transducers are useful for writing to or reading from magnetic data-storage media. Conventionally, inductive transducers write binary-formatted data to a moving magnetic storage medium, such as a rotating magnetic disc, by imparting a bipolar magnetic pattern representing the binary data to the medium. Because current flowing in a conductor generates a magnetic field according to its direction of flow, producing the bipolar magnetic pattern entails forcing current through an inductive coil in forward and reverse directions corresponding to the binary data. Applying the resulting fields to the magnetic disc coerces a series of magnetic dipoles into alignment with the fields to form the bipolar magnetic pattern.

A write driver controls current flow through the inductive coil. Write drivers for two-terminal inductive coils usually comprise four switches operated as switching pairs to control current flow in the coil. Activating one pair directs current flow in a first direction through the: coil, and activating the other pair directs current flow in a second and opposite direction. This switching arrangement is known as an H-bridge, or H-switch, because the four switches and the coil operate in an "H-like" formation. With the coil forming the bar of the "H" and the switches forming two vertical line segments, the switching pairs direct current along the diagonals of the "H", giving rise to the term diagonal pairs. Although this basic form of the H-bridge requires four control signals, i.e. one per switch, to control current flow, it is common, because of the pairing, to use only two. Additionally, such switching systems (commonly use transistors operating between conductive (activated) and nonconductive states as switches. FIG. 1 shows a prior art write driver having an H-bridge with only two control signals.

In the prior art write driver, four transistors Q₁, Q₂, Q₃, and Q₄ and inductive coil L form an H-bridge connected between voltage source V_(CC) and current source I_(W). Current source I_(W) is coupled to voltage source V_(EE), which is at ground potential. Transistors Q₁ and Q₂ form a first diagonal pair, and transistors Q₃ and Q₄ form a second. Transistors Q₁ and Q₄ have their collectors connected to voltage source V_(CC) and their emitters connected to the respective collectors of transistors Q₃ and Q₂. The emitters of transistors Q₂ and Q₃ are coupled together and to current source I_(W). Because of the high current switched by transistors Q₁ -Q₄, these transistors are large devices. PNP-type transistors Q₉ and Q₁₀ form a differential pair which controls the H-bridge by switching current source I₂ according to the lower of inputs W_(D) and W_(DN) applied to the respective bases of transistors Q₉ and Q₁₀.

When input W_(D) is lower than input W_(DN) transistor Q₁₀ conducts current I₂ from source I₂, raising collector potential V_(C10) of transistor Q₁₀ to V_(EE) +(I_(C10) -I_(B8))R₁, where V_(EE), I_(C1), and I_(B2) respectively denote the voltage of source V_(EE), the collector current of transistor Q₁₀, and the base current of transistor Q₈. Transistor Q₈ is thereby activated. Transistor Q₈, configured as an emitter-follower, has its base connected to the collector of transistor Q₁₀, its collector connected to voltage source V_(CC), and its emitter corrected to the bases of transistors Q₂ and Q₆ and to voltage source V_(EE) via resistor R₄. Thus, when transistor Q₈ is activated, a portion of its emitter current I_(E8) flows through resistor R₄ and into the bases of transistors Q₂ and Q₆. That portion of the emitter current I_(E8) flowing through resistor R₄ raises the base potentials V_(B2) and V_(B6) of respective transistors Q₂ and Q₆ to a voltage sufficient to activate those transistors. When activated, transistor Q₆ draws collector current I_(C6) through resistor R₂, which is connected between a collector of transistor Q₆ and voltage source V_(CC). Collector current I_(C6) generates a voltage across resistor R₂ that deactivates transistor Q₄.

When input W_(DN) is higher than input W_(D), transistor Q₉, connected between current source I₂ and resistor R₅, does not conduct. Because resistor R₅ is coupled to voltage source V_(EE) and transistor Q₉ is nonconductive, collector potential V_(C9) of transistor Q₉ decreases to V_(EE). Transistor Q₇ has its base connected to the collector of transistor Q₉, its collector connected to source V_(CC), and its emitter connected to the bases of transistors Q₃ and Q₅ and to source V_(EE) through resistor R₃. Thus, when transistor Q₉ is nonconductive, base potentials V_(B7), V_(B5), and V_(B3) of respective transistors Q₇, Q₅, and Q₃ fall to V_(EE), thereby deactivating transistors Q₇, Q₅, and Q₃. Transistor Q₅ has its emitter connected to the emitter of transistor Q₆ and to the positive terminal of current source I₁, and its collector connected to the base of transistor Q₁ and to source V_(CC) via resistor R₁. Hence, when transistor Q₅ is deactivated, resistor R₁ conducts no collector current I_(C5). As a consequence, base potential V_(B1) of transistor Q₁ rises to V_(CC), activating transistor Q₁. Accordingly, the first diagonal pair conducts current I_(W), causing coil L to generate a magnetic field having a first polarity.

Reversing polarity of the field entails deactivating the first diagonal pair (transistors Q₁ and Q₂) and activating the second diagonal pair by switching inputs W_(DN) and W_(D) from high to low and low to high, respectively. Operating input W_(DN) low activates transistors Q₉, Q₇, Q₅, and Q₃, and deactivates transistor Q₁, and operating input W_(D) high deactivates transistors Q₁₀, Q₈, Q₆, and Q₂ and activates transistor Q₄. Thus, the second diagonal pair, consisting of transistors Q₃ and Q₄, conducts current I_(W) in a second direction through coil L, thereby generating a field having a second polarity, opposite the first. Therefore, selectively switching inputs W_(D) and W_(DN) alternately directs current I_(W) through the coil to write a specific bipolar magnetic pattern on a magnetic medium.

Although the prior art driver of FIG. 1 ideally functions as described, it operates under practical switching limitations inherent to bipolar junction transistors. Unlike ideal switches, bipolar junction transistors have parasitic base-to-collector (BTC) capacitances that preclude instantaneous changes between conductive (activated) and nonconductive states. Because they are slow to charge and discharge, BTC capacitances appreciably prolong, or delay, transitions between these states, thereby inhibiting rapid switching of the H-bridge. In particular, because transistor pairs Q₂ -Q₆ and Q₃ -Q₅ are larger devices, they have larger BTC capacitances than the other transistors of the prior art driver. Thus, they more seriously impact the switching efficiency of the write driver. The time they require for charging and discharging limits the write frequency of the transducer and the storage density of the medium. The limitation becomes especially acute during a magnetic field reversal when the charging and discharging times are cumulative.

Reversing the magnetic field entails switching both diagonal pairs. One pair switches from nonconducting to conducting and the other from conducting to nonconducting. In FIG. 1, the BTC capacitances of transistor pairs Q₂ -Q₆ and Q₃ -Q₅ charge and discharge by the respective base currents I_(B2-6) and I_(B3-5). Transistors Q₈ and Q₇ supply these base currents by their respective emitters. Although transistors Q₈ and Q₇ are good sources of current, much of the current they supply sinks through resistors R₄ and R₃, respectively. That which supplies the bases of transistor pairs Q₂ -Q₆ and (Q₃ -Q₅ is not sufficient to avoid stewing the output of the transducer.

Discharging the BTC capacitances of transistor pairs Q₂ -Q₆ and Q₃ -Q₅ occurs passively by sinking base currents I_(B2-6) and I_(B3-5) through respective resistors R₄ and R₃ to source V_(EE) . Currents sinking through resistors R₄ and R₃ produce I-R voltages that support the base potentials of respective transistor pairs Q₂ -Q₆ and Q₃ -Q₅. Supporting these base potentials prolongs the conductive states of the transistor pairs during discharge, thereby preventing current I_(W) from switching when desired. Moreover, a portion of the discharge as well as inductive kickback enters the bases of the switching transistors, causing momentary conductive surges in the switching transistors. These momentary surges cause glitching in the output of the transducer. Thus, passive discharging introduces further slewing and causes glitching in the output of the transducer Although reducing resistors R₃ and R₄ would speed the rate of discharge, it would also increase the power needs of the driver without solving the glitching problem. In sum, limitations in sourcing and sinking the base currents of transistor pairs Q₂ -Q₆ and Q₃ -Q₅ cause appreciable slewing and glitching, generally degrading the quality of data written to a medium, increasing the time required to write data, and restricting the storage density of the medium.

SUMMARY OF THE INVENTION

A write driver for a two-terminal inductive load comprises a transistor H-bridge switching circuit and a push-pull driver circuit. The H-bridge switching circuit responds to a first mode to conduct a current in a first direction through the inductive load and responds to a second mode to conduct the current in a second direction through the inductive load. The push-pull driver circuit responds to the first mode to push a charge current into a first control node of the H-bridge and responds to the second mode to pull at discharge current from the first control node.

In one form of the invention, the write driver includes a second push-pull driver circuit responsive to the first mode to pull a discharge current from a second control node of the H-bridge and to the second mode to push a charge current into the second control node. By providing the charge and discharge currents to the respective first and second control nodes, the push-pull driver charges and discharges parasitic capacitance associated with these nodes.

Another aspect of the present invention is a method of charging and discharging parasitic BTC capacitances of first and second differentially-paired transistors. A charge current is actively pushed into the base of the first transistor while a discharge current is actively pulled from the base of the second transistor. Preferably, a charge current is also actively pushed into the base of the second transistor while a discharge current is actively pulled from the base of the first transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a prior art write driver circuit.

FIG. 2 is a schematic diagram of a writ(, driver circuit according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 2 shows a write driver for a two-terminal inductive load, according to the present invention. Four transistors Q₁, Q₂, Q₃, and Q₄ and inductive coil L form an H-bridge connected between voltage source V_(CC) and current source I_(W) coupled to voltage source V_(EE). Transistors Q₁ and Q₂ form a first diagonal pair, and transistors Q₃ and Q₄ form a second. Transistors Q₁ and Q₄ have collectors connected to voltage source V_(CC) and emitters connected to the respective collectors of transistors Q₃ and Q₂. The emitters of transistors Q₂ and Q₃ are coupled together and to current source I_(W). Because of the large current conducted by transistors Q₁ -Q₄, these transistors are large devices with significant BTC capacitances. Transistors Q₂ and Q₃ are Schottky transistors, which by design are unsaturable. Transistors Q₅ and Q₆ form a first emitter-coupled differential pair which switches current source I_(W) to one or the other side of the differential pair according to which transistor Q₅ or Q₆ has the higher base voltage. The respective bases of transistors Q₅ and Q₆ are coupled to the bases of transistors Q₃ and Q₂, forming two control nodes N₁ and N₂ of the H-bridge. The collectors of transistors Q₅ and Q₆ are connected to the bases of transistors Q₁ and Q₄ and to source V_(CC) via resistors R₁ and R₂.

Transistors Q₇ and Q₈, configured as emitter-followers, are respectively coupled between source V_(CC) and the bases of transistors Q₅ and Q₆ Transistors Q₁₁, and Q₁₂ are PNP transistors coupled between the respective emitters of transistors Q₇ and Q₈ and voltage source V_(EE). The base of transistor Q₇ is coupled to current source I₃ and to the collector of PNP transistor Q₁₃, and the base of transistor Q₈ is coupled to current source I₄ and to the collector of PNP transistor Q₁₄. Transistors Q₁₃ and Q₁₄, forming a second emitter-coupled differential pair, control current source I₂ according to which has the lower base voltage. In other words, current source I₂ follows the lower of inputs W_(D) or W_(DN). Configured as diodes, transistors Q₁₅ and Q₁₆ are coupled respectively between transistors Q₁₃ and Q₁₇ and transistors Q₁₄ and Q₁₈. PNP transistors Q₁₇ and Q₁₈, also configured as diodes, are coupled via their collectors to respective diodes D₁ and D₂ and via their bases to respective transistors Q₁₁ and Q₁₂. Diodes D₁ and D₂ are parallel-coupled to respective resistors R₇ and R₈, which are connected to source V_(EE) through respective resistors 1% and R₁₀. Because diodes D₁ and D₂ are Schottky diodes, i.e. majority-carrier devices without diffusion capacitances, they switch on and off very quickly.

Transistors Q₈, Q₁₂ and Q₇, Q₁₁ form respective first and second push-pull (also termed class-B or complementary) driver stages of the write driver. Current source I₄ continuously supplies a bias current I₄ to diode-configured transistors Q₁₆ and Q₁₈ thereby maintaining a constant forward-biasing voltage across the base-emitter junctions of transistors Q₈ and Q₁₂. Accordingly, transistors Q₈, Q₁₂, Q₁₆, Q₁₈ form a translinear loop defined by

    V.sub.BE8 +V.sub.BE12 =V.sub.BE16 +V.sub.BE18,

where V_(BE) denotes the base-emitter voltage of the respective transistor. The biasing provided by transistors Q₁₆ and Q₁₈ and current source I₄ alleviate cross-over distortion inherent to switching between the positive and negative sides of the first class-B driver. Taken together, the class-B driver and the biasing circuitry constitute a class-AB driver, because both transistors Q₈ and Q₁₂ remain active throughout operation of the write driver. Base voltage V_(B18) of transistor Q₁₈ serves as the input to the class-AB driver. Thus, when base voltage V_(B18) becomes more positive than its bias, or quiescent, value fixed by resistors R₈ and R₁₀ and bias current I₄, base-emitter voltage V_(BE12) decreases and base-emitter voltage V_(BE8) increases to maintain equality with the sum V_(BE16) +V_(BE18). Transistor Q₈ therefore conducts, or pushes, a load current into control node N₂. When base voltage V_(B18) becomes negative, base-emitter voltage V_(BE10) increases and base-emitter voltage V_(BE8) decreases an equal amount so that transistor Q₁₀ conducts, or pulls, a load current from control node N₁.

Likewise, current source I₃ supplies a continuous bias current I₃ to diode-configured transistors Q₁₅ and Q₁₇ to maintain a constant forward-biasing voltage across the base-emitter junctions of transistors Q₇ and Q₁₁. Consequently,

    V.sub.BE7 +V.sub.BE11 =V.sub.BE15 +V.sub.BE17,

where V_(BE) denotes the base-emitter voltages of the respective transistors. The biasing provided by transistors Q₁₅ and Q₁₇ and current source I₁₃ alleviates cross-over distortion inherent to switching between the positive and negative sides of the second class-B driver comprising transistors Q₇, Q₁₁. Taken together, the second class-B driver and its biasing circuitry constitute a second class-AB driver. Base voltage V_(B) ₁₇ of transistor Q₁₇ serves as the input to the second class-AB driver. The second class-AB driver operates identically to the first. Moreover, to facilitate symmetrical operation, transistors Q₇, Q₁₅ and Q₈, Q₁₆ form matched NPN pairs, and transistors Q₁₁, Q₁₇ and Q₁₂, Q₁₈ form matched PNP pairs. Bias currents I₃ and I₄ and resistors R₇ and R₈ yield voltages which are less than the turn-on thresholds of diodes D₁ and D₂.

Operatively, when input W_(D) is lower than input W_(DN), transistors Q₁₄, Q₁₆, and Q₁₈, and resistors R₈ and R₁₀ conduct current I₂ from current source I₂. Current I₂ and resistor R₈ generate a voltage exceeding the threshold voltage of diode D₂ (approximately 600 millivolts), thereby activating diode D₂. Base voltage V_(B18) of transistor Q₁₈ thus rises to V_(EF) +(I₂)R₁₀ +V_(D2), where V_(EE) and V_(D2) respectively denote a voltage level of source V_(EE) and a voltage across diode D₂. When diode D₂ activates, its voltage V_(D2) reduces the base-emitter voltage V_(BE12), increasing base-emitter voltage V_(BE8) and forcing transistor Q₈ to conduct a load current into control node N₂. The load current quickly charges the BTC capacitances of transistors Q₂ and Q₆ and drives them to full conductivity. In turn, transistor Q₆ draws collector current I_(C6) (approximately equal to current I₁) through resistor R₂ connected between a collector of transistor Q₆ and voltage source V_(CC). Collector current I_(C6) generates a voltage across resistor R₂ that deactivates transistor Q₄.

Because input W_(DN) is higher than input V_(D), transistor Q₁₃ cannot conduct current I₂. Transistors Q₇, Q₁, Q₁₅, and Q₁₇ are conducting bias current I₃. Diode D₁ is inactive; so the base voltage of transistor Q₁₁ is V_(EE) +I₃ (R₇ +R₉). Base-emitter voltage V_(BE11) therefore remains unchanged and transistor Q₁₁ pulls a load current from control node N₁. This load current quickly deactivates transistors Q₃ and Q₅ by discharging their BTC capacitances. Transistor Q₅ conducts no current through resistor R₁. Thus, base voltage V_(B1) of transistor Q₁ rises to V_(CC), thereby activating transistor Q₁. Accordingly, the first diagonal pair (transistors Q₁ and Q₂) conducts current I_(W) (right to left) through coil L, causing it to generate a magnetic field having a first polarity.

Reversing polarity of the field entails deactivating the first diagonal pair and activating the second diagonal pair by switching inputs W_(DN) and W_(D). Operating input W_(DN) low activates diode D₁ which causes transistor Q₇ to push a load current into control node N₁. Pushing the load current into control node N₁ quickly charges the BTC capacitances of transistors Q₃ and Q₅ and deactivates transistor Q₁. On the other hand, operating input W_(D) high deactivates diode D₂ which causes transistor Q₁₂ to pull a load current from node N₂, thereby rapidly discharging the BTC capacitances of transistors Q₂ and Q₆ and activating transistor Q₄. Thus, the second diagonal pair consisting of transistors Q₃ and Q₄ conducts write current I_(W) in a second direction (left to right) through coil L. This current generates a field having a second polarity, opposite the first. Hence, switching inputs W_(D) and W_(DN) alternates the direction of current I_(W) through the coil to write a specific bipolar magnetic pattern on a magnetic medium.

The present invention overcomes the switching limitations of the prior write drivers. More particularly, during a first mode, the first class-AB driver actively pushes a charge current into control nod N₁ of the H-bridge, and the second class-AB driver pulls a discharge current from control node N₂, thereby rapidly charging the BTC capacitances of transistor pair Q₂ -Q₆ and discharging the BTC capacitances of transistor pair Q₃ -Q₅. In a second mode, the second class-AB driver pushes a charge current into control node N₂, and the first class-AB driver pulls a discharge current from control node N₁. The present invention further promotes rapid switching by replacing resistors R₃ and R₄ of the prior art with respective transistors Q₁₁ and Q₁₂. This substitution reduces the impedance seen by nodes N₁ and N₂ during discharge and precludes the discharge currents from supporting the base potentials of transistors Q₂ -Q₆ and Q₃ -Q₅ during deactivation, thereby further improving switching performance. It also prevents inductive kickback from entering the bases of the switching transistors and causing glitching in the transducer output. In sum, a first mode urges rapid switching of the H-bridge by activating the first class-AB driver to source current to the first control node and the second class-AB driver to sink a current from the second control node of the H-bridge. A second mode urges rapid switching by enabling the second class-AB driver to source current to the second control node and enabling the first class-AB driver to sink a current from the first control node.

Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention. 

What is claimed is:
 1. A write driver switching system for supplying current to a two-terminal inductive load, comprising:a switching circuit having first and second switching transistors each connected between a first supply terminal and respective first and second load terminals, the first and second load terminals for connecting to the inductive load, the first and second switching transistors being responsive to write signals at respective first and second control nodes for driving current in first and second directions through the inductive load; a driver circuit having a first drive transistor coupled between the first control node and the first supply terminal and a second drive transistor coupled between the first control node and a second supply terminal; a bias circuit for maintaining the second drive transistor in a conductive state during operation of the switching circuit, the bias circuit coupled to a control terminal of the second drive transistor and the first and second supply terminals and, the bias circuit including:first and second diodes connected in series between respective control terminals of the first and second drive transistors; and a bias current source connected between the first diode and the second supply terminal; control means responsive to write signals for alternately operating the first and second drive transistors to selectively charge and discharge a capacitance of the first switching transistor; and a third diode parallel-coupled to a resistor, the resistor connected between the second diode and the first supply terminal.
 2. The write driver of claim 1 further comprising:a second driver circuit having a first transistor coupled between the second control node and the first supply terminal and a second transistor coupled between the second control node and the second supply terminal.
 3. The write driver switching system of claim 1 wherein the third diode is a Schottky diode.
 4. In a switching circuit having a pair of load terminals for connecting to a magnetic transducer, a switching transistor connected between one of the load terminals and a first supply terminal, and a driver circuit comprising:a first transistor having a pair of controlled terminals connected between a control terminal of the switching transistor and the first supply terminal for actively discharging a capacitance of the switching transistor to the first supply terminal; a second transistor having a pair of controlled terminals connected between the control terminal of the switching transistor and a second supply terminal for actively charging the capacitance of the switching transistor, one of the pair of controlled terminals of the first transistor being connected to one of the pair of controlled terminals of the second transistor; constant bias means for maintaining the first and second transistors in a conductive state during operation of the switching circuit, the constant bias means including:first and second diodes connected in series between respective control terminals of the first and second transistors; and a bias current source connected between the second supply terminal and the first diode; and input means responsive to write signals for increasing conductivity of one of the first and second transistors the input means including a third diode parallel-coupled to a resistor the resistor connected between the second diode and the first supply terminal.
 5. The driver circuit of claim 4 wherein the third diode is a Schottky diode. 